RISC-V Performance Soars to New Heights

Taking Flight at

Taking Flight at

0
0
0
0
Days
0
0
Hrs
0
0
Min
0
0
Sec

Engineered for what comes next

Condor Computing is a U.S.-based R&D subsidiary of Andes Technology, established in 2023 in Austin, Texas, to push the boundaries of open, high-performance, computing. Condor was created with a singular mission: To design the world’s most advanced RISC-V processor IP — from the ground up.

While Andes has long been recognized for power-efficient, highly configurable cores, Condor was established to extend that legacy into performance-driven domains.

Our Mission

Condor’s charter is to architect and design next-generation RISC-V processor IP that delivers uncompromising performance, power efficiency, and innovation — enabling our partners to compete at the frontier of AI, cloud, and data-centric computing.

Who We Are

  • R&D Powerhouse: Our team consists of senior CPU architects and silicon veterans with decades of experience building world-class microarchitectures.

  • U.S Based Design: Entirely developed in the U.S., Condor offers an alternative to IP developed off-shore — enabling customers with greater insight, control, and compliance.

  • Backed by Andes: With Andes’ established history of customer support of embedded and configurable RISC-V IP, Condor is uniquely positioned to scale quickly and deliver to customers with confidence.

Why It Matters

As AI, HPC, and edge workloads become more demanding, the world needs an open, scalable compute foundation that’s not tied to legacy architectures. Condor’s roadmap is designed to fill that gap — enabling real-world performance without compromise

Why It Matters

As AI, HPC, and edge workloads become more demanding, the world needs an open, scalable compute foundation that’s not tied to legacy architectures. Condor’s roadmap is designed to fill that gap — enabling real-world performance without compromise

Our Technology

At Condor Computing, we’re not just building processor IP — we’re redefining what’s possible with open instruction set computing. Our architecture is a clean-sheet, out-of-order RISC-V microarchitecture designed to achieve best-in-class performance and power efficiency for today’s most demanding workloads —from AI inference to high-throughput computing in the cloud.

Breakthrough Microarchitecture

Our upcoming processor IP is built around a highly scalable, deeply out-of-order pipeline with the following hallmarks:

  • Our Novel Temporal Instruction Management: Predicts optimal issue timing to reduce power and area waste

  • 8-Issue Superscalar Design: Aggressive instruction throughput with deep speculation

  • Advanced Branch Prediction & Prefetching: Minimize latency across complex workloads

  • Scalable Memory Hierarchy: Designed for both edge compute and large-scale server-class systems
  • RISC-V Compliant: Full support for the latest RISC-V profiles for modern application environments

Performance, Meet Practicality

Unlike many clean-sheet architectures, Condor’s CPUs are engineered for integration and usability:

  • Designed to run within the Andes software ecosystem

  • Compatible with industry-standard EDA flows

  • Validated through full-system emulation and real benchmarks

  • Delivered with a robust, industry-proven toolchain and software stack support

We’re actively working with early partners and will disclose more benchmarks, performance data, and architectural details in upcoming conferences and technical sessions. For early engagement customers, contact us at condor-riscv@andestech.com

Come see us at