Ty is the President and Founder of Condor Computing. Most recently, he was the VP of Engineering at Mythic, where he led the development of the first neural network accelerator based on analog computation. Previously, Ty was CTO at Arteris IP, and he led worldwide IC design teams at Intel/Altera and TI.  In days past, Ty participated in the development of microprocessors and SoCs at ARM, MIPS, Motorola, Cyrix and Alchemy.  Ty has more than 40 US patents granted.

Thang is a specialist in microprocessor architecture and design. Before joining Condor Computing as CTO, Thang had 40+ years of experience at Motorola, AMD, Intel, ADI, Centaur Technologies, TI, MediaTek, Freescale, Synopsys, and Andes Technology. His notable microprocessors include AMD Athlon, ARM Cortex-A8, and NX27V. He also has taught microprocessor design at Viet Nam National University in Ho Chi Minh City, and Computer Architecture at Santa Clara University. Thang received his MBA from St. Edwards University in 1985 and his Ph.D. ECE from University of Texas at Austin in 1992. Dr. Tran has 165+ granted patents, with many more pending patent applications.

Tracy is a seasoned finance and operations management professional experienced in many industries, including semiconductor IP licensing, venture capital, renewable energy, and high-performance multimedia storage. Before Condor Computing, Tracy served as VP of Operations and Finance at SIC USA, and she was the Corporate Controller of Kilopass Technology. Tracy has extensive experience partnering with CEOs/COOs to lead finance and operations for organizational growth in a variety of business stages.

Shashank Nemawarkar has contributed to compute architectures for servers and mobile devices over 25 years with more than 40 patents from concept to production designs including IBM PowerPC processors, Newisys x86 SMP servers-a first for AMD, and Samsung Exynos processors. Previously, at GlobalFoundries CTO office, he guided customers and academic collaborators on full stack optimization from applications and architectures to technologies to achieve power-performance-area goals. His Ph.D. from McGill University in Montreal on multithreaded architectures (SMT) formed the basis of his contributions to efficient, high throughput compute, network processors, coherent node controllers and SSD controllers designs. He has an M.Tech. from IIT Kanpur and a B.E.(Hons) from BITS Pilani.

Paul has most recently focused on implementation of the advanced 4D digital radar systems developed by Uhnder. Previously he contributed to the development of multiple generations of CPU and DSP systems for Qualcomm, AMD/Alchemy, Ross Technologies and Kendall Square Research. Paul received degrees from MIT and Texas A&M.

Doug brings to Condor his over 35 years of experience verifying high performance microprocessors and SoCs. He has led multinational teams to first-pass success at several companies including Intel, Oracle Labs, and AMD. At Intel, Doug led the verification efforts of several subsystems that reside on the next-generation Xeon processor SoCs. At Oracle Labs, Doug’s team verified a high-performance database acceleration engine. Prior to that, Doug was at AMD, where he led the verification efforts for both the Bobcat x86 core and AMD’s first APU SoC.

Trevor has over 30 years semiconductor management experience leading teams to successfully deliver high performance enterprise solutions. These products included Sparc and RISC-V processors, 10Gb & 40Gb converged network adapters, and the highest performance NVMe flash controllers. His startups included Ross Technology, ServerEngines (acquired by Emulex), Mangstor, and InspireSemi. Trevor has BSc in Physics and Electronics from the University of Manchester.